Hardware Debug - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID
PG034
Release Date
2022-05-18
Version
4.1 English

Some of the common problems encountered and possible solutions follow.

You have programmed your BD ring but nothing seems to work.

Register programming sequence has to be followed to start the CDMA. See Programming Sequence.

Internal Error/Error bits set in the Status register.

Internal error could be set when BTT specified in the descriptor is 0. SG internal error would be set if the fetched BD is a completed BD. Other error bits like Decode Error or Slave Error could also be set based on the response from Interconnect or Slave.

You are reading data from a location, but the data does not seem to be in order.

Verify if the start address location is aligned or un-aligned. If it is un-aligned, ensure that the DRE is enabled while configuring CDMA.