Simulation - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID
PG034
Release Date
2022-05-18
Version
4.1 English

For comprehensive information about Vivado simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 5].

 

IMPORTANT:   For cores targeting 7 series or Zynq®-7000 devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only.