Additional Considerations - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

Design limitations of the SEM core include the following:

EasyPath™ devices are not compatible with the error correction by replace method.

The SEM Controller initializes and manages the FPGA integrated silicon features for soft error mitigation. When the controller is included in a design, do not include any design constraints or options that would enable the built-in detection functions. Enabling the necessary functions to provide detection is performed autonomously by the SEM Controller. For example, do not set POST_CRC, POST_CONFIG_CRC, or any other related constraints. Similarly, do not include options to disable GLUTMASK. The default value of YES is required to prevent false error detections by the SEM core.

Software computed ECC and CRC values are not supported.

Simulation of designs that instantiate the controller is supported. However, it is not possible to observe the controller behaviors in simulation. Simulation of a design including the controller compiles, but the controller does not exit the initialization state. Hardware-based evaluation of the controller behaviors is required.

Use of SelectMAP persistence is not supported by the controller.

When the controller requires storage of configuration data for correction by replace, this data must be available to the controller through the Fetch Interface, typically through the EXT shim. This decouples the controller from the FPGA configuration method and allows customers flexibility in selection of configuration method, configuration data storage, and soft error mitigation solution data storage.

The EXT shim implementation supports only one SPI flash read command (fast read) in SPI Mode 0 (CPOL = 0, CPHA = 0) to a single SPI flash device.

Due to potential I/O voltage incompatibility between the FPGA and standard SPI flash devices, level translation might be required in the design of the SPI memory system.

ICAP Arbitration and ICAP Switchover are not supported. Only a single ICAP instance is supported, and it must reside at the primary/top physical location.

Use of design capture, including the use of the capture primitive and related functionality, is not supported by the controller.

Controller implementations for 7 series FPGAs and Zynq-7000 SoCs operate on soft errors in Type 0, Type 2, and Type 3 configuration frames. See the Xilinx 7 Series FPGA Configuration User Guide , for information on these configuration frame types [Ref 1] .

SEM controller does not operate when a golden or fallback bitstream is loaded by a configuration error and fallback condition from a SPI/BPI flash. See AR: 67645 .