Clock Interface - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The Clock Interface is used to provide a clock to the system-level design example. Internally, the clock signal is distributed on a global clock buffer to all synchronous logic cells.

Table 5-2: Clock Interface Details

Name

Sense

Direction

Description

clk

EDGE

IN

Receives the master clock for the system-level design example.