Clocking - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

Xilinx recommends the clock to be sourced from an oscillator and brought in from a pin directly to the SEM controller. While the likelihood of an SEU event hitting the configuration cells associated with creating the clock internally from a PLL or DCM is very small, it is best to strive for the highest reliability possible. However, if a PLL or DCM output or other logic is used to generate the clock, ensure the clock never violates the SEM controller minimum period at any time, including during design start up or prior to PLL/DCM lock.

When clock management is used, suppress the clock toggling to the SEM controller until after the clock is stable. For example use a BUFGMUX or BUFGCE to keep the SEM controller clock from toggling until PLL/DCM lock is achieved.