This section includes information about using Xilinx® tools to customize and generate the core in the Vivado Design Suite. To customize and generate the core, locate the IP core in the Vivado IP catalog at FPGA Features and Design > Soft Error Mitigation > Soft Error Mitigation and click it once to select it. Important information regarding the solution is displayed in the Details pane of the Project Manager window. Review this information before proceeding.
Double-click the IP core in the IP catalog to open the customization dialog box, shown in This Figure .
Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current version.
Review each of the available options, and modify them as desired so that the SEM Controller solution meets the requirements of the larger project into which it is integrated. The following sub-sections discuss the options in detail to serve as a guide.