When using optional features such as error correction by replacement and error classification, the controller requires access to externally stored data. This data is created by write_bitstream at the same time the programming file for the FPGA is created. The files are related.
Any time the FPGA design is changed and a new programming file is created, the additional data files used by the controller must also be updated. When the hardware design is updated with the new programming file, the externally stored data must also be updated.
IMPORTANT: Failure to maintain data consistency can result in unpredictable controller behavior. AMD recommends use of an update methodology which ensures that the programming file and the additional data files are always synchronized.