Error Correction Latency - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

After detecting an error, the solution attempts correction. Errors are correctable depending on the selected correction mode and error type. Table: Non-SSI: Max Error Correction Latency (100 MHz) No Throttling on Monitor Interface and Table: SSI: Max Error Correction Latency (70 MHz) No Throttling on Monitor Interface provide error correction latency for a configuration frame upset, assuming no throttling on the Monitor Interface.

Table 2-5: Non-SSI: Max Error Correction Latency (100 MHz) No Throttling on Monitor Interface

Correction
Mode

Errors in Frame (Correctability)

Error Correction State at ICAP_F Max

Repair

1-bit (Correctable)

610 µs

2-bit (Uncorrectable)

25 µs

Enhanced Repair

1-bit (Correctable)

610 µs

2-bit (Correctable)

18,790 µs

2-bit (Uncorrectable)

9,110 µs

BFR (1) -only (Uncorrectable)

10 µs

Replace

Any (Correctable)

830 µs

Any

CRC-only (Uncorrectable)

10 µs

Notes:

1. BFR is an error condition due to a multi-bit upset in an enhanced repair checksum stored in block RAM.

Table 2-6: SSI: Max Error Correction Latency (70 MHz) No Throttling on Monitor Interface

Correction
Mode

Errors in Frame (Correctability)

Error Correction State at ICAP_F Max

Repair

1-bit (Correctable)

915 µs

2-bit (Uncorrectable)

70 µs

Enhanced Repair

1-bit (Correctable)

910 µs

2-bit (Correctable)

26,900 µs

2-bit (Uncorrectable)

13,010 µs

BFR (1) -only (Uncorrectable)

10 µs

Replace

Any (Correctable)

1,220 µs

Any

CRC-only (Uncorrectable)

10 µs

Notes:

1. BFR is an error condition due to a multi-bit upset in an enhanced repair checksum stored in block RAM.

The error correction latency at the actual frequency of operation can be estimated using data from Table: Non-SSI: Max Error Correction Latency (100 MHz) No Throttling on Monitor Interface and This Equation .

Equation 2-3 pg036_product_spec00006.jpg