Error Detection Latency - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

Error detection latency is the major component of the total error mitigation latency. Error detection latency is a function of the FPGA size (frame count) and the solution clock frequency. It is also a function of the type of error and the relative position of the error with respect to the position of the silicon readback process. Table: Maximum Device Scan Times at ICAP FMax illustrates full device scan times.

Table 2-4: Maximum Device Scan Times at ICAP F Max

Device

Scan Time at ICAP F Max

XC7A12T

2.6 ms

XC7A15T

4.6 ms

XC7A25T

2.6 ms

XC7A35T

4.6 ms

XC7A50T

4.6 ms

XC7A75T

8.0 ms

XC7A100T

8.0 ms

XC7A200T

18.3 ms

XC7K70T

5.9 ms

XC7K160T

12.9 ms

XC7K325T

23.5 ms

XC7K355T

26.5 ms

XC7K410T

30.3 ms

XC7K420T

35.3 ms

XC7K480T

35.3 ms

XC7VX330T

25.6 ms

XC7VX415T

32.5 ms

XC7VX485T

38.3 ms

XC7VX550T

54.1 ms

XC7VH580T (SSI)

24.6 ms

XC7V585T

41.2 ms

XC7VX690T

54.1 ms

XC7VH870T (SSI)

24.6 ms

XC7VX980T

70.7 ms

XC7VX1140T (SSI)

24.6 ms

XC7V2000T (SSI)

31.6 ms

XC7Z007S

4.0 ms

XC7Z012S

7.2 ms

XC7Z014S

8.0 ms

XC7Z010

4.0 ms

XC7Z015

7.2 ms

XC7Z020

8.0 ms

XC7Z030

11.3 ms

XC7Z035

27.2 ms

XC7Z045

27.2 ms

XC7Z100

34.3 ms

XC7S6

1.3 ms

XC7S15

1.3 ms

XC7S25

2.6 ms

XC7S50

4.6 ms

XC7S75

8.0 ms

XC7S100

8.0 ms

The device scan time for the target device, at the actual frequency of operation, can be estimated using data from Table: Maximum Device Scan Times at ICAP FMax and This Equation .

Equation 2-2 pg036_product_spec00004.jpg

The error detection latency can be bounded as follows:

Absolute minimum error detection latency is effectively zero.

Average error detection latency for detection by ECC is 0.5 × Scan Time ACTUAL

Maximum error detection latency for detection by ECC is Scan Time ACTUAL

Absolute maximum error detection latency for detection by CRC alone is 2.0 × Scan Time ACTUAL

The frame-based ECC method used always detects single, double, triple, and all odd-count bit errors in a frame. The remaining error types are usually detected by the frame-based ECC method as well. It is rare to encounter an error that defeats the ECC and is detected by CRC alone.