Features - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The SEM controller includes:

Integration of silicon features to leverage built-in error detection capability.

Implementation of error correction capability to support correction of soft errors. The error correction method can be defined as:

° Repair : ECC algorithm-based correction. This method supports correction of configuration memory frames with single-bit errors. This covers correction of all single-bit upset events. It also covers correction of multi-bit upset events when errors are distributed one per frame as a result of configuration memory interleaving.

° Enhanced Repair : ECC and CRC algorithm-based correction. This method supports correction of configuration memory frames with single-bit errors or double-bit adjacent errors. This covers correction of all single-bit upset events and all double-bit adjacent upset events. This also covers correction of multi-bit upset events when errors are distributed one or two adjacent per frame as a result of configuration memory interleaving.

° Replace : Data reload based correction. This method supports correction of configuration memory frames with arbitrary errors. This covers correction of any upset event that can be resolved to specific configuration memory frames, even if the exact bit locations in the frames cannot be determined.

Implementation of error classification capability to determine if corrected errors have affected configuration memory in locations essential to the function of the design.

Provision for error injection to support verification of the controller and evaluation of applications of the controller.

The example design includes:

Instantiation of the user-configured controller.

An interface between the controller and external storage. This is required when the controller is configured to perform error classification or error correction by replace.

An interface between the controller and an external processor for ease of use when the controller is configured to perform error injection.