ICAP Interface - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The ICAP Interface is a point-to-point connection between the SEM Controller and the ICAP primitive. The ICAP primitive enables read and write access to the registers inside the FPGA configuration system. The ICAP primitive and the behavior of the signals on this interface are described in the 7 Series FPGAs Configuration User Guide (UG470) [Ref 1] .

Table 2-15: ICAP Interface Signals

Name

Sense

I/O

Description

icap_o[icap_width-1:0]

HIGH

I

Receives O output of ICAP. The variable icap_width is equal to 32.

icap_csib

LOW

O

Drives CSIB input of ICAP.

icap_rdwrb

LOW

O

Drives RDWRB input of ICAP.

icap_i[icap_width-1:0]

HIGH

O

Drives I input of ICAP. The variable icap_width is equal to 32.

icap_clk

EDGE

I

Receives the clock for the design. This same clock also must be applied to the CLK input of ICAP. The clock frequency must comply with the ICAP input clock requirements as specified in the target device data sheet.

icap_request

HIGH

O

This signal is reserved for future use. Leave this port OPEN.

icap_grant

HIGH

I

Tie this port to VCC. Receives an ICAP initialization grant signal from the user. icap_grant can be used to hold off the controller initialization state.