Port Descriptions - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

This Figure shows the example design ports for non-SSI devices. The ports are clustered into six groups. The groups shaded in gray only exist in certain configurations.

Figure 5-3: Example Design Ports

X-Ref Target - Figure 5-3

ex_design_ports_x12176.jpg

In an SSI device, each super logic region (SLR) is numbered. There are two numbering methods: hardware SLR numbering and software SLR numbering.

A hardware SLR number represents the configuration order of the SLR in the device. The Master SLR, which is always present, is hardware SLR 0. The hardware SLR numbers of additional Slave SLRs are approximately assigned radially outward from the Master SLR.

A controller instance located in an SLR determines the hardware SLR number at runtime by reading the IDCODE register through the internal configuration access port (ICAP) on that SLR. In all command and status exchanges with controllers implemented in an SSI device, hardware SLR numbering is used.

A software SLR number represents the bottom-to-top physical order of the SLR in the device. The Master SLR, which is always present, has a software SLR number that varies by device. The software SLR numbers are prominently visible in the device view presented by the Xilinx® development software.

Table: Device SLR Numbers details the mapping between hardware SLR numbers and software SLR numbers.

Table 5-1: Device SLR Numbers

Device

Software SLR Number

Hardware SLR Number

SLR Type

XC7VH580T

2

X

GTZ

1

1

SLAVE

0

0

MASTER

XC7VH870T

4

X

GTZ

3

2

SLAVE

2

0

MASTER

1

1

SLAVE

0

X

GTZ

XC7VX1140T

3

3

SLAVE

2

2

SLAVE

1

0

MASTER

0

1

SLAVE

XC7V2000T

3

3

SLAVE

2

2

SLAVE

1

0

MASTER

0

1

SLAVE

TIP: Understanding and translating the SLR numbering methods is not necessary for successful implementation of controllers in an SSI device. However, this information might be useful in conjunction with error injection if it is desired to direct an injected error to a specific SLR.

This Figure shows the example design ports for SSI devices. The ports are clustered into six groups. The groups shaded in gray only exist in certain configurations. In SSI devices, the Status Interface ports become buses, where the bus width is determined by the number of SLRs in the SSI device.

Figure 5-4: Example Design Ports for SSI Devices

X-Ref Target - Figure 5-4

pg036_ex_design_ports_x12176.jpg

The system-level design example has no reset input or output. The controller automatically initializes itself. The controller then initializes the shims, as required.

The system-level design example is a fully synchronous design using clk as the single clock. All state elements are synchronous to the rising edge of this clock. As a result, the interfaces are generally synchronous to the rising edge of this clock.