Revision History - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The following table shows the revision history for this document.

Date

Version

Revision

05/04/2022

4.1

Updated Configuration Memory Masking section.

04/04/2018

4.1

Added Key Considerations for SEM IP Adoption section in Overview chapter.

Updated to remove obsolete method of calculating FIT in Solution Reliability section in Product Specification chapter.

04/05/2017

4.1

Added Encryption and Authentication Support section.

Added Spartan-7 data to ICAP Maximum Frequencies to Maximum Device Scan Times at ICAP FMax tables.

Added Zynq data to Resource Utilization for Zynq-7000 Devices table.

Added Artix-7 data to Resource Utilization for Artix-7 Devices table.

Added Resource Utilization for Spartan-7 Devices table.

Added Artix, Spartan, and Zynq data for External Storage Requirements table.

Added AR to Additional Considerations section.

Updated code examples for Creating the External Memory Programming File for Non-SSI Devices and Creating the External Memory Programming File for SSI Devices sections.

Updated description in Interface Debug section.

09/30/2015

4.1

Updated Maximum Start-Up Latency at ICAP Fmax table.

Added User Parameter and Integration and Validation sections in Design Flow Steps chapter.

11/19/2014

4.1

Added resource utilization and performance metrics for new Artix-7 (XC7A15T) and Zynq-7000 (XC7Z035) devices.

Updated text to indicate bitstream encryption is supported.

Corrected status_heartbeat specification to indicate a maximum of 150 cycles between heartbeat pulses.

04/02/2014

4.1

Updated core to v4.1.

Replaced legacy ChipScope support with Vivado Lab Tools support.

Added resource utilization and performance metrics for new Artix-7 and Zynq-7000 devices.

Updated instructions to execute makedata.tcl script.

Added Synthesis and Implementation section.

06/19/2013

4.0

Updated instructions to execute makedata.tcl script in Implementation .

Updated resource utilization for Virtex-7 SSI devices in Resource Utilization .

Added solution latencies for Zynq-7000 7Z100 devices in Solution Latency .

Added more information about possible system-level supervisory functions in Designing with the Core .

03/20/2013

4.0

Updated core to v4.0.

Removed support for ISE Design Suite.

Increased the maximum clock frequency to 100 MHz for select 7 series devices.

12/18/2012

3.0

Updated core to v3.4, ISE Design Suite to v14.4 and Vivado Design Suite to v2012.4.

Added pre-production support for Zynq-7000, Artix-7, and Virtex-7 SSI devices.

Redesigned the Spartan-6 solution based on new guidance for configuration readback.

07/25/2012

2.0

Added support for Vivado Design Suite.

04/24/2012

1.0

Initial Xilinx release. Replaces DS796, LogiCORE IP Soft Error Mitigation Controller Data Sheet, and UG764, LogiCORE IP Soft Error Mitigation Controller User Guide .