SPI Bus Clock Waveform and Timing Budget - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The SPI flash device has requirements on the switching characteristics of its input clock. This analysis is for the clock signal generated for the SPI flash device by the system-level design example. Completion of this analysis requires board-level signal integrity simulation capability.

Figure 3-7: SPI Flash Device Input Clock Requirements

X-Ref Target - Figure 3-7

spiclk_input.jpg

The following parameters, shown in This Figure , are defined as requirements on the clock input to the SPI flash device:

T clch = SPI bus clock maximum rise time requirement

T chcl = SPI bus clock maximum fall time requirement

T cl = SPI bus clock minimum low time requirement

T ch = SPI bus clock minimum high time requirement

Based on the physical construction of the SPI bus, the I/O characteristics of the FPGA, and the I/O characteristics of any level translator used, the SPI bus clock signal originating at the FPGA exhibits maximum rise and fall times (T rise and T fall ) at the SPI flash device. Satisfaction of T clch and T chcl requirements by T rise and T fall must be verified. Should T clch and T chcl requirements not be satisfied, avenues of correction include:

Change I/O slew rate for the system-level design example SPI bus clock output.

Change I/O drive strength for the system-level design example SPI bus clock output.

Select an alternate level translator with more suitable I/O characteristics.

Generally, the T clch and T chcl requirements are easy to satisfy. They exist to prohibit exceptionally long rise and fall times that might occur on a true bus with many loads, rather than the point-to-point scheme used with the system-level design example.

The SPI bus clock generated by the system-level design example is the input clock divided by two. Therefore, the SPI bus clock high and low times are nominally equal to T clk . However, considering actual T rise and T fall , also ensure satisfaction of the following:

T clk T rise + T ch

T clk T fall + T cl

Example :

T clch = 33 ns (from SPI flash data sheet)

T chcl = 33 ns (from SPI flash data sheet)

T cl = 9 ns (from SPI flash data sheet)

T ch = 9 ns (from SPI flash data sheet)

T rise = 2 ns (from PCB simulation)

T fall = 2 ns (from PCB simulation)

Given this data, perform the following:

1. Check: Is T clch T rise ? Is 33 ns 2 ns? Yes

2. Check: Is T chcl T fall ? Is 33 ns 2 ns? Yes

3. Calculate: T clk T rise + T ch requires T clk 2 ns + 9 ns, or T clk 11 ns

4. Calculate: T clk T fall + Tcl requires T clk 2 ns + 9 ns, or T clk 11 ns

The rise time requirements are satisfied. These requirements on T clk indicate that the SPI Bus Clock Waveform and Timing Budget restrict the system-level design example input clock cycle time to be 11 ns or larger.