SPI Bus Timing Budget Conclusions - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

When the EXT shim and external memory system are present, the SPI bus timing budget must be analyzed to ensure a robust implementation. The result of the analysis confirms that the external memory system is functional, and reveal any constraints it might pose on the maximum frequency of the system-level design example input clock.

Example Conclusion

Using the example data from the Vivado® Design Suite timing report for a Kintex®-7 SEM IP implementation, the memory interface is functional. The most stringent requirement on Tclk is that Tclk 14.512 ns, as the memory interface only works when the input clock frequency is 68.908 MHz or lower. Other input clock frequency limits, such as the internal configuration access port (ICAP) maximum clock frequency and the system-level example maximum clock frequency, must also be considered.