Sample Latency Estimation - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

Document ID
PG036
Release Date
2022-05-04
Version
4.1 English

The first sample estimation illustrates the calculation of error mitigation latency for a single-bit error by the solution implemented in an XC7K325T device with a 66 MHz clock. The solution is configured for error correction by repair, with error classification disabled. The initial assumption is that no throttling occurs on the Monitor Interface.

Equation 2-6 pg036_product_spec00012.jpg

Equation 2-7 pg036_product_spec00014.jpg

Equation 2-8 pg036_product_spec00016.jpg

Equation 2-9 pg036_product_spec00018.jpg

The second sample estimation illustrates the calculation of error mitigation latency for a two-bit error by the solution implemented in an XC7K325T device with a 66 MHz clock. The solution is configured for error correction by replace, with error classification enabled. Again, it is assumed that no throttling occurs on the Monitor Interface.

Equation 2-10 pg036_product_spec00020.jpg

Equation 2-11 pg036_product_spec00022.jpg

Equation 2-12 pg036_product_spec00024.jpg

Equation 2-13 pg036_product_spec00026.jpg

The final sample estimation illustrates an assessment of the additional latency that would result from throttling on the Monitor Interface. Assume the message length in both the first and second samples is approximately 80 bytes, but the buffer depth of the MON Shim is 32 bytes. Further, the MON Shim has been modified to raise the bit rate from 9600 baud to 460800 baud. The standard 8-N-1 protocol used requires 10 bit times on the serial link to transmit a 1-byte payload:

Equation 2-14 pg036_product_spec00028.jpg

This result illustrates that the additional latency resulting from throttling on the Monitor Interface can become significant, especially when the data transmission is serialized and the data rate is low.