ARESETn - 5.0 English

Video In to AXI4-Stream LogiCORE IP Product Guide (PG043)

Document ID
PG043
Release Date
2021-10-22
Version
5.0 English

The ARESETN pin is an active-Low reset, which is synchronous to the ACLK domain. When the bridge is in independent clock mode, this reset is used to reset the AXI4-Stream input side of the video bridge including the internal FIFO. Asserting either this reset causes the internal FIFO to be reset. In common clock mode this reset is used to reset the entire bridge.