The FIFO depth is selectable via the GUI when the core is generated. The buffering requirement for the asynchronous FIFO depends mainly on the relative frequency of the AXI4-Stream clock ( aclk ) to the video clock ( vid_io_in_clk ) frequency, and the line standard used.
If the frequency of the AXI4-Stream clock ( Faclk ) is equal to or greater than the frequency of the Video input pixel clock ( Fvclk ), only the minimum buffer size (32 locations) is required. This assumes that the cores connected downstream of the Video In to AXI4-Stream core can sink data at the full video rate. For example, the downstream core can accept data in a virtually continuous stream with gaps occurring only following EOL , and each line consecutively with line gaps only preceding SOF . In this scenario, the FIFO empties after the EOL on each line.
If Faclk is less than Fvclk , additional buffering may be required. The FIFO must store enough pixels to supply them continuously throughout the active line. Due to phasing requirements, the horizontal active period on the output could overlap the effective blanking period of pixels coming in from the AXI4-Stream bus. This means that the input FIFO must also be large enough to provide output pixels continuously during this time.
For AXI4-Stream clock frequencies above the line average but below that of the video input pixel clock, the minimum FIFO initial fill level must be:
FIFO depth min. = 32+ Active Pixels * Fvclk / Faclk
If the downstream processing core accepts data at a lower rate than the AXI4-Stream clock, Additional buffering is required in an amount sufficient to prevent the FIFO from overflowing during the course of a frame.