There are two clocking modes used by the Video In to AXI4-Stream bridge, either common (synchronous) or independent (asynchronous). The common clocking mode is used when the native and AXI4-Stream sides of the bridge are running from a common synchronous clock. The common clocking mode disables the clock domain crossing logic in the internal FIFO, therefore saving resources. The independent clocking mode is used when the bridge requires asynchronous and independent clocks for the native and AXI4-Stream sides of the bridge.
The video input clock corresponds to the video line standard used on the input. It is part of the video line standard and is used by both the Video In to AXI4-Stream core and by the corresponding Video Timing Controller core that is used to detect video timing.
The AXI4-Stream clock ( aclk ) is part of the AXI4-Stream bus. To minimize buffering requirements, this clock should be of equal or higher frequency than the video input clock. This clock can be slower than the video input clock, in which case, additional buffering is required to store pixels so that lines can be input at the burst rate of the video clock. This is discussed in the Buffer Requirements section. At a minimum, the aclk frequency must be higher than the average pixel rate.