The Video In to AXI4-Stream core converts a video input, consisting of parallel video data, video syncs, blanks and data valid, to an AXI4-Stream master bus that follows the AXI4-Stream Video protocol. The core provides a pass-through of all timing signals for the Xilinx video timing controller, although the signals for the Video timing Controller are not required to pass through the Video In to AXI4 Stream core.
The core handles the asynchronous clock boundary crossing between the video clock domain and the AXI4-Stream clock domain. The data width is selectable from 8 to 256 depending on the number of components required for the video format, the number of bits per component, and the number of pixels per clock. Interlaced operation is supported. There is an input FIFO with selectable depth from 32 to 8192 locations.