• Video input (clocked parallel video data with synchronization signals - active video with either syncs, blanks or both)
• AXI4-Stream master interface
• Interface to Xilinx Video Timing Controller core for video timing detection
• Support for common or independent clock modes between AXI4-Stream and video clock domains
• Selectable FIFO depth from 32–8192 locations
• Selectable input data width of 8–256 bits
• Support for interlaced operation
• Component width conversion for 8, 10, 12, and 16 bits
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LogiCORE IP Facts Table |
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Core Specifics |
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Versal™ devices, UltraScale+™ Families, UltraScale™ Architecture, Zynq ® -7000 SoC, 7 Series |
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Supported User Interfaces |
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Resources |
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Provided with Core |
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Documentation |
Product Guide |
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Design Files |
Verilog Source Code |
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Example Design |
Provided Separately
(
3
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Test Bench |
Verilog |
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Constraints File |
XDC |
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Simulation Models |
Verilog Source Code |
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Supported Software Drivers |
N/A |
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Tested Design Flows |
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Design Entry Tools |
Vivado ® Design Suite |
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For supported simulators, see the
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Synthesis Tools |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54538 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. Video protocol as defined in the Video IP: AXI Feature Adoption section of (UG761) AXI Reference Guide [Ref 4] . 3. Example designs are provided in FPGA device-specific application notes
4.
For the supported versions of the tools, see the
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