General Design Guidelines - 5.0 English

Video In to AXI4-Stream LogiCORE IP Product Guide (PG043)

Document ID
PG043
Release Date
2021-10-22
Version
5.0 English

The video inputs of the Video In to AXI4 Stream core should be connected to the input video source; for example, a DVI interface chip that produces parallel video data and timing signals. Not all of the timing signals are required by this core. However, the core passes these signals to a Xilinx Video Timing Controller which, depending on its configuration, may require certain timing signals. Use the set of timing signals required by the VTC detector. See the Video Timing Controller Product Guide (PG016) [Ref 8] for more details. For the Video In to AXI4 Stream core, the data valid ( vid_active_video ) signal is always required. Also, either a vertical sync or a vertical blank input is required.

The main output of the core is a master AXI4-Stream bus that connects to downstream video processing blocks as shown in This Figure . The master and slave interfaces share a common clock, reset, and clock enable.

As shown in This Figure , the Video In to AXI4 Stream Core is generally used in conjunction with the Video Timing Controller, which detects the video timing parameters used by downstream processing blocks.

Figure 3-1: Video In to AXI4-Stream Connectivity

X-Ref Target - Figure 3-1

pg043_3_1_x13205.jpg