When the downstream processing block on the AXI4-Stream bus can take data at the pixel rate or faster, the typical latency through the Video In to AXI4-Stream core is 6 cycles of vid_io_in_clk + 3 cycles of aclk .
If the downstream block takes pixels at a slower rate, the FIFO is used to balance the mismatch in the input and output rates over the course of lines and frames. This storage of pixels in the FIFO adds to the latency and varies according to the data flow in and out of the core.