Many Xilinx ® video processing cores utilize the AXI4-Stream video protocol to transfer video between cores. Between systems, video is commonly transmitted with explicit blanking and sync signals for horizontal and vertical timing, and a data valid signal. Digital visual interface (DVI) is an example of such a transmission mode. The Video In to AXI4-Stream core converts incoming video with explicit sync and timing to the AXI4-Stream Video protocol to interface with Xilinx video processing cores that use this protocol.
The Video In to AXI4-Stream core accepts video inputs. For this document, video is defined as parallel video data with a pixel clock and one of the following sets of timing signals:
• Vsync, Hsync, and Data Valid
• Vblank, Hblank, and Data Valid
• Vsync, Hsync, Vbank, Hblank, and Data Valid
Any of these sets of signals is sufficient for the operation of the Video In to AXI4-Stream core. The particular choice is important to the Video Timing Controller (VTC) detector, so you should specify the set of timing signals when you generate the VTC core. The output side of the core is an AXI4-Stream interface in master mode. This interface consists of parallel video data, tdata , handshaking signals tvalid and tready , and two flags, tlast and tuser , which identify certain pixels in the video stream. The flag tlast designates the last valid pixel of each line, and is also known as end of line ( EOL ). The flag tuser designates the first valid pixel of a frame, and is known as start of frame ( SOF ). These two flags are necessary to identify pixel locations on the AXI4 stream bus because there are no sync or blank signals. Only active pixels are carried on the bus. The Video IP: AXI Feature Adoption section of the AXI Reference Guide [Ref 4] describes the video over AXI4 Stream Video protocol in detail.
A block diagram of a Video In to AXI4-Stream core with a video timing generator is shown in This Figure .
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X-Ref Target - Figure 1-1 
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The core is designed to be used in parallel with the detector functionality of the VTC. The video timing detector detects the line standard of the incoming video, and makes the detected timing values, such as the number of active pixels per line and the number of active lines available to video processing cores downstream of the Video In to AXI4-Stream core via an AXI4-Lite interface. It is recommended to connect the “locked” status output of the video timing detector to the axis_enable input of the Video In to AXI4-Stream core in order to inhibit the AXI4-Stream bus when the video input is missing or unstable. The detector locked indicator from the Video Timing Controller is bit 8 of the INTC_if register.
Note: When the video clock is not present, for example, when an input cable is unplugged. Ensure to reset the VTC and Video In to AXI4-Stream cores. If these cores are not reset, locked signal goes high and it might allow partial frames down stream. Therefore, Xilinx recommends that you reset the VTC and Video In to AXI4-Stream cores when the video clock is not available.