The read logic controls the handshake for the AXI4-Stream bus and provides pixels to this bus as rapidly as possible. In general, the strategy for AXI4-Stream is downstream-greedy. That is, downstream modules take pixels as soon as they are available and there is buffer space to accommodate them. Since the Video In to AXI4-Stream core is at the front of the pipeline, it strives to empty its FIFO as fast as possible.
The Read Logic controls the tvalid handshaking signal based on the level and flags from the FIFO, and the tready signal returned from the downstream module. Whenever data is available in the FIFO, tvalid is asserted. When tready is returned active, the FIFO is read and the new pixel is again denoted by the tvalid being active. Thus, the tvalid is asserted except when there is no valid data available from the FIFO. The FIFO will only begin filling if the downstream core cannot accept data as fast as it is coming in from the video bus. This will happen, for example, if the AXI4-Stream clock, aclk , is slower than the video clock. In this case, during the active portion of each line, pixels will be coming into the FIFO faster than they can be sent out on the AXI4-Stream bus. Thus the FIFO will begin to fill. Usually the FIFO will empty at the end of the active line when the downstream core is still taking pixels, but the incoming video data is in the horizontal blanking period.