When the core is in common clock mode, there is only a single reset input port aresetn that is used to reset both the AXI4-Stream output and Video input sides of the bridge. In independent clock mode, an additional reset port vid_io_in_reset is used to reset the Video output side of the bridge. To reset the entire core in independent clock mode, both resets much be asserted. In independent clock mode, both resets are OR'ed together and synchronized for the purpose of resetting the FIFO; therefore, asserting either reset causes the FIFO to be flushed. Resets must be synchronous to their respective clock domains. The bridge requires that resets be externally synchronized to the destination clock domain as necessary to avoid metastability. When asserted, the reset should be held for at least two clock periods of the lowest frequency clock.