The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
10/22/2021 |
5.0 |
• Added Versal™ devices. • Updated description in Video Data . • Updated Customize IP . |
|
03/17/2021 |
4.0 |
• Added a note for input-output order in Product Specification. • Removed Test Bench section as it is not supported. |
|
12/17/2019 |
4.0 |
• Added a note in the Overview chapter. • Updated Figures 3-5, 3-6, and 3-7. • Removed Timing Mode, Slave Mode, Master Mode, and Master Mode with Fsynch sections from Chapter 3. |
|
10/04/2017 |
4.0 |
• Added clock domain for field-id signals • Updated vid_io_in_reset signal information. |
|
11/18/2015 |
4.0 |
Added UltraScale+ support. |
|
09/30/2015 |
4.0 |
Updated System Clocking and Resets. |
|
04/01/2014 |
3.0 |
Added support for multiple pixels per clock. |
|
12/18/2013 |
3.0 |
Added UltraScale Architecture support. |
|
10/02/2013 |
3.0 |
• Sync document version with core version. • Updated Constraints and Migration chapters. |
|
03/20/2013 |
4.0 |
• Updated for core version. Removed ISE chapters. • Updated Debugging appendix. • Updated Core Interfaces. Updated Designing with the Core chapter. |
|
10/16/2012 |
3.0 |
• Updated for core version. • Updated for ISE v14.3 and Vivado v2012.3. • Added Vivado test bench. |
|
07/25/2012 |
2.0 |
• Updated for core version. • Added Vivado information. |
|
04/24/2012 |
1.0 |
Initial Xilinx release of core. |