The average data rates of active pixels on the AXI4-Stream interface matches the average rate of active pixels in on the Video bus. However, the clock rates of the input and output need not match. Because the AXI4-Stream bus does not carry blank pixels, the clock rate can be lower than the video clock rate and still have sufficient bandwidth to meet the average rate requirement. Additional FIFO depth is required to smooth the mismatch in instantaneous rates. Both the input video pixel clock ( Fvclk ) and the rate of the AXI4-Stream Clock ( Faclk ) are limited by the overall Fmax .
If Faclk is equal to or greater than Fvclk , only the minimum buffer size (32 locations) is required. This assumes that the cores connected downstream of the Video In to AXI4-Stream core can sink data at the full video rate. For example, the downstream core can accept data in a virtually continuous stream with gaps occurring only following EOL , and each line consecutively with line gaps only preceding SOF . In this scenario, the FIFO empties after the EOL on each line.
If Faclk is less than Fvclk , additional buffering is required. The FIFO must be large enough to handle the differential in the rate that pixels are coming in on the video clock, and the slower rate that they can go out on the AXI4-Stream bus using aclk . For aclk frequencies above the line average but below that of vclk , the input FIFO depth must be:
FIFO depth min = 32 + Active Pixels * Fvclk/Faclk
If the downstream processing core accepts data at a lower rate than the aclk , additional buffering is required in an amount sufficient to prevent the FIFO from overflowing during frame transmission.