The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, if video data widths are not an integer multiple of 8, data must be padded with zeros on the MSB to form an N*8-bit wide vector before connecting to m_axis_video_tdata . Padding does not affect the size of the core.
Similarly, data on the Video in to AXI4-Stream output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. This Figure shows an example of this for 12-bit RGB data for one pixel per clock. For multiple pixels per clock, the pixels are packed together and packed to multiples of 8 bits as necessary. This Figure shows an example of three pixels per clock with 12-bit per component RGB data. Although this is the expected packing, the core itself does not parse the data. In other words, the AXI4-Stream output will be the video input padded to a multiple of 8 bits.
The bridge is also able to perform component width conversion from the input to output for any combination of width including: 8, 10, 12, and 16 bit. The example shown in This Figure illustrates trimming the component width from 12 bits on Video Input to 8 bits on the AXI4-Stream output. The four LSB's of each component are trimmed and the remaining data is packed onto the output video bus.
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X-Ref Target - Figure 2-4 
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The example shown in This Figure illustrates padding the component width from 8 bits on Video Input to 12 bits on the AXI4-Stream output. The four LSB's on the output of each component are padded to zeros and the upper MSB's are mapped onto the bus from the Video Input.
