Aurora 8B/10B Simplex Normal Operation Reset Sequence - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID
PG046
Release Date
2023-10-19
Version
11.1 English

For the simplex configuration, it is recommended that the TX side reset sequence is tightly coupled with the RX side reset sequence because the TX and RX links do not have a communication feedback path. Note that if the RX side is reset, there is no direct mechanism to notify the TX side of the reset. Hence, for Aurora 8B/10B simplex cores, reset coupling needs to be handled at the system level. Every TX-side reset must be followed by the RX-side and, as shown in This Figure, the time between RX-side reset deassertion and TX-side reset deassertion must be kept as minimal as possible. Before asserting gt_reset, a minimum of 128 clock time period is required for ensuring that the portion of the core in programmable logic reaches a known reset state before the user_clk is suppressed by the assertion of gt_reset. The assertion time of gt_reset must be a minimum of six init_clk time periods, to satisfy the de-bouncing circuit included in the core.

Figure 3-8:      Aurora 8B/10B Simplex Normal Operation Reset Sequence

X-Ref Target - Figure 3-8

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