Clock compensation is a feature allowing up to ±100 ppm difference in the reference clock frequencies used on each side of an Aurora 8B/10B channel. A standard clock compensation module <component_name>_standard_cc_module.v[hd] is generated with the core in accordance with the Aurora 8B/10B Protocol Specification (SP002) [Ref 5].
The standard_cc_module handles the periodicity of generation of the clock compensation character as described in Table: Clock Compensation Cycles. The periodicity can be controlled with CC_FREQ_FACTOR.
|
Lane Width |
USER_CLK Cycles Between DO_CC |
DO_CC Duration (USER_CLK cycles) |
|---|---|---|
|
2 |
5,000 |
6 |
|
4 |
2,500 |
3 |
The number of lookahead cycles required to prevent a 16-byte UFC message from colliding with a clock compensation sequence depends on the number of lanes in the channel and the width of each lane.
Native flow control message requests are not acknowledged during clock compensation character transmission. This helps to prevent the collision of an NFC message and the clock compensation sequence.
IMPORTANT: The parameter CC_FREQ_FACTOR determines the frequency of the CC sequence. Any attempt to increase or decrease the parameter should be done with careful analysis and testing.
•Be sure the duration and period selected is sufficient to correct for the maximum difference between the frequencies of the clocks that are used.
•Do not perform multiple clock correction sequences within eight cycles of one another.
•Replacing long sequences of idles (>12 cycles) with CC sequences can reduce EMI.