The Aurora 8B/10B core example design clock constraints can be grouped into following three categories:
•GT reference clock constraint
The Aurora 8B/10B core example design uses a minimum of one and a maximum of two reference clocks. The number of GT reference clocks is dependent upon the transceiver selection. The GT REFCLK value selected on the first page of the Vivado IDE is used to constrain the GT reference clock using the create_clock XDC command.
Note: For UltraScale devices, the GT reference clock location constraint should be added to <user_component_name>_example.xdc.
•TXOUTCLK clock constraint
TXOUTCLK is generated by the transceiver based on the input reference clock and the divider settings of the transceiver. The create_clock XDC command is used to constrain TXOUTCLK.
•INIT CLK constraint
The Aurora 8B/10B core example design uses a debounce circuit to sample GT_RESET which is clocked asynchronously by the system clock. The create_clock XDC command is used to constrain the system clock.
RECOMMENDED: Use a system clock frequency lower than the GT reference clock frequency.