Clocking from Neighboring Transceiver Quads - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID
PG046
Release Date
2023-10-19
Version
11.1 English

The AMD implementation tools make the necessary adjustments to the north-south routing and pin swapping to the transceiver clock inputs to route clocks from one quad to another, when required.

 

IMPORTANT:   The following rules must be observed when sharing a reference clock to ensure that jitter margins for high-speed designs are met:

The total number of GTX or GTH transceiver quads sourced by an external clock pin pair (mgtrefclkn/mgtrefclkp) in 7 series FPGAs must not exceed three quads (one quad above and one quad below), or 12 GTXE2_CHANNEL/GTHE2_CHANNEL transceivers. Designs with more than 12 transceivers or more than three quads in 7 series FPGAs should use multiple external clock pins.

The total number of transceiver quads sourced by an external clock pin pair (mgtrefclkn/mgtrefclkp) in UltraScale architecture FPGAs must not exceed five quads (two quads above and two quads below), or 20 GTHE3_CHANNEL transceivers.

 

 

IMPORTANT:   Manual edits are not recommended, but are possible using the recommendations in the UltraScale FPGAs GTH Transceivers User Guide (UG576) [Ref 1] and 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 3].