Design Flow Steps - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID
PG046
Release Date
2023-10-19
Version
11.1 English

This chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the standard design flows and the AMD Vivado™ IP integrator can be found in these Vivado Design Suite user guides:

Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 6]

Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 7]

Vivado Design Suite User Guide: Getting Started (UG910) [Ref 8]

Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 9]