This Figure shows an example of a simple data transfer on an AXI4-Stream interface that is n-bytes wide. In this case, the amount of data being sent is 3n bytes and so requires three data beats. s_axi_tx_tready is asserted, indicating that the AXI4-Stream interface is ready to transmit data.
The user application asserts s_axi_tx_tvalid during the first n bytes to begin data transfer. An /SCP/ ordered set is placed on the first two bytes of the channel to indicate the start of the frame. Then the first n–2 data bytes are placed on the channel. Because of the offset required for the /SCP/, the last two bytes in each data beat are always delayed one cycle and transmitted on the first two bytes of the next beat of the channel.
To end the data transfer, the user application asserts s_axi_tx_tlast, the last data bytes, and the appropriate value on the s_axi_tx_tkeep bus. In this example, s_axi_tx_tkeep is set to N in the waveform for the demonstration to indicate that all bytes are valid in the last data beat. When s_axi_tx_tlast is asserted, s_axi_tx_tready is deasserted in the next clock cycle and the core uses the gap in the data flow to send the final offset data bytes and the /ECP/ ordered set, indicating the end of the frame. s_axi_tx_tready is reasserted on the next cycle to allow data transfers to continue.
