There are two factors that affect framing efficiency in the Aurora 8B/10B core:
•Size of the frame
•Width of the datapath
The CC sequence, which uses 12 bytes on every lane every 10,000 bytes, consumes about 0.12% of the total channel bandwidth.
All bytes in the Aurora 8B/10B core are sent in two-byte code groups. Aurora 8B/10B frames with an even number of bytes have four bytes of overhead, two bytes for SCP (start of frame) and two bytes for ECP (end of frame). Aurora 8B/10B frames with an odd number of bytes have five bytes of overhead, four bytes of framing overhead plus an additional byte for the pad byte.
The core transmits frame delimiters only in specific lanes of the channel. SCP is only transmitted in the left-most (most-significant) lane, and ECP is only transmitted in the right-most (least-significant) lane. Any space in the channel between the last code group with data and the ECP code group is padded with idles. The result is reduced resource cost for the design, at the expense of a minimal additional throughput cost. Though the SCP and ECP could be optimized for additional throughput, the single frame per cycle limitation imposed by the user interface would make this improvement unusable in most cases.
Use the formula shown in This Equation to calculate the efficiency for a design of any number of lanes, any width of interface, and frames of any number of bytes.
Note: This formula includes the overhead for clock compensation.
Where:
°E = The average efficiency of a specified PDU
°n = Number of user data bytes
°12n/9988 = Clock correction overhead
°4 = Overhead of SCP + ECP
°0.5 = Average PAD overhead
°IDLEs = Overhead for IDLEs = (w/2) – 1
°w = Interface width
Table: Efficiency Example is an example calculated from This Equation. It shows the efficiency for an 8-byte, 4-lane channel and illustrates that the efficiency increases as the length of channel frames increases.
Table: Typical Overhead for Transmitting 256 Data Bytes shows the overhead in an 8-byte, 4-lane channel when transmitting 256 bytes of frame data across the four lanes. The resulting data unit is 264 bytes long due to start and end characters, and due to the idles necessary to fill out the lanes. This amounts to 3.03% of overhead in the transmitter. In addition, a 12-byte clock compensation sequence occurs on each lane every 10,000 bytes, which adds a small amount more to the overhead. The receiver can handle a slightly more efficient data stream because it does not require any idle pattern.
Table: Value of s_axi_tx_tkeep and Corresponding Bytes of Overhead shows the overhead that occurs with each value of s_axi_tx_tkeep.
Note: When the Little Endian option is selected in the Vivado Integrated Design Environment (IDE), s_axi_tx_tkeep bit ordering changes from MSB to LSB.