The transceiver attributes play a vital role in the functionality of the Aurora 8B/10B core. Use the latest Transceiver Wizard to generate the transceiver wrapper file.
RECOMMENDED: AMD strongly recommends that the transceiver wrapper file is updated in the AMD Vivado™ Design Suite tool releases when the transceiver wizard has been updated but the Aurora core has not.
This appendix provides instructions to generate these transceiver wrapper files.
Use these steps to generate the transceiver wrapper file using the 7 series FPGAs transceivers wizard:
1.Using the Vivado IP catalog, run the latest version of the 7 Series FPGAs Transceivers Wizard. Make sure the Component Name of the transceiver wizard matches the Component Name of the Aurora 8B/10B core.
2.Select the protocol template from the following based on the number of lane(s) and lane width:
°Aurora 8B/10B single lane 2 byte
°Aurora 8B/10B single lane 4 byte
°Aurora 8B/10B multi lane 2 byte
°Aurora 8B/10B multi lane 4 byte
3.Change the Line Rate in both TX and RX based on the application requirement.
4.Select the Reference Clock from the drop-down menu in both TX and RX based on the application requirement.
5.Select transceiver(s) and the clock source(s) based on the application requirement.
6.Keep the default for all other settings.
7.Generate the core.
8.Replace the <component name>_gt.v[hd] and <component name>_
multi_gt.v[hd] files in the gt directory available in the Aurora 8B/10B core with the generated <component name>_gt.v[hd] and <component name>_
multi_gt.v[hd] files generated from the 7 series FPGAs transceivers wizard.
The transceiver settings for the Aurora 8B/10B core are now up to date.
Note: The UltraScale™ architecture Aurora 8B/10B core uses the hierarchical core calling method to call the UltraScale device gtwizard IP core. In this way, all the transceiver attributes, parameters, and required workarounds are in place and correct. Manual editing of the UltraScale device transceiver files are not required in most of the cases. The attribute(s) in the Aurora 8B/10B core example design XDC file can be updated.