Latency through an Aurora 8B/10B core is caused by pipeline delays through the protocol engine (PE) and through the transceivers. The PE pipeline delay increases as the AXI4-Stream interface width increases. The transceiver delays are dependent on the features and attributes of the selected transceivers.
This section outlines expected latency for the Aurora 8B/10B core AXI4-Stream user interface in terms of user_clk cycles for 2-byte-per-lane and 4-byte-per-lane designs. For the purposes of illustrating latency, the Aurora 8B/10B modules are partitioned into transceiver logic and protocol engine (PE) logic which is implemented in the FPGA programmable logic.
Note: These numbers do not include the latency incurred due to the length of the serial connection between each side of the Aurora 8B/10B channel.
This Figure illustrates the latency of the datapath for the default configuration. Latency can vary based on the transceiver(s) used in the design and the IP configuration.
Minimum latency for a two-byte framing design from s_axi_tx_tvalid to m_axi_rx_tvalid is approximately 37 user_clk cycles in functional simulation for the default core configuration (see This Figure).
Minimum latency for a default four-byte framing design from s_axi_tx_tvalid to m_axi_rx_tvalid is approximately 41 user_clk cycles in functional simulation.
The pipeline delays are designed to maintain the clock speed. If there is no dependency, check if the latency can be added through other optional features.