This guide describes how to generate an AMD LogiCORE™ IP Aurora 8B/10B core using AMD UltraScale™ and UltraScale+™ family GTH transceivers, AMD Kintex™ 7, Virtex™ 7 FPGA GTX and GTH transceivers, AMD Artix™ 7 FPGA GTP transceivers, and AMD Zynq™ 7000 device GTX and GTP transceivers. The Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface.
The AMD Vivado™ Design Suite produces source code for Aurora 8B/10B cores with a configurable datapath width. The cores can be simplex or full-duplex, and feature one of two simple user interfaces and optional flow control.
The Aurora 8B/10B core (This Figure) is a scalable, lightweight, link-layer protocol for high-speed serial communication. The protocol is open and can be implemented using AMD FPGA technology. The protocol is typically used in applications requiring simple, low-cost, high-rate, data channels and is used to transfer data between devices using one or many transceivers.
Aurora 8B/10B cores automatically initialize a channel when they are connected to an Aurora channel partner and pass data freely across the channel as frames or streams of data. Aurora frames can be any size, and can be interrupted at any time. Gaps between valid data bytes are automatically filled with idles to maintain lock and prevent excessive electromagnetic interference. Flow control can be used to reduce the rate of incoming data or to send brief, high-priority messages through the channel.
Streams are single, unending frames. In the absence of data, idles are transmitted to keep the link alive. The Aurora 8B/10B core detects single-bit and most multi-bit errors using 8B/10B coding rules. Excessive bit errors, disconnections, or equipment failures cause the core to reset and attempt to re-initialize a new channel.
RECOMMENDED: Although the Aurora 8B/10B core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, experience building high-performance, pipelined FPGA designs using AMD implementation tools and constraints files (XDC) with the Vivado Design Suite is recommended. Read Status, Control, and the Transceiver Interface, carefully.
Consult the PCB design requirements information in:
•UltraScale FPGAs GTH Transceivers User Guide (UG576) [Ref 1]
•7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 2]
•7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 3]
Contact your local AMD representative for a closer review and estimation for your specific requirements.