The major change to the core is the addition of the AXI4-Stream interface:
•Flow control interface ports mapped to the standard AXI4-Stream interface.
•Single-ended clock option added to core init_clk and gt_refclk.
•GT selection option for the UltraScale device added to the core.
•All reset inputs made asynchronous.
•Standard CC module made part of IP; do_cc and warn_cc ports removed.
•Single-ended clocking option added to the core when shared logic is in the core.
•All core input and output ports grouped as interfaces.
•Line rate value restricted to 4 decimal digits for UltraScale devices.
•INIT clock frequency value restricted to 6 decimal digits.