Port Descriptions - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID
PG046
Release Date
2023-10-19
Version
11.1 English

The parameters used to generate each Aurora 8B/10B core determine the interfaces available for that specific core. The interfaces are visible in the IP symbol as seen in This Figure. In the IP symbol, if you left-click the + sign beside the interface, you can see the ports grouped in it. In this section, that is, Port Descriptions, in general, the interface appears as a single row entry followed by the ports which are grouped in it. For example in Table: User I/O Ports (TX) (TX) the USER_DATA_S_AXIS_TX is the interface and the s_axi_tx_* ports are grouped into that interface. The cores have four to six interfaces.

Figure 2-4:      IP Top-Level Interface

X-Ref Target - Figure 2-4

Figure_2-4_Top-Level_Interface.PNG

Notes:

1.[n:0] bus format is used when the Little Endian Support option is selected.

2.[0:n] bus format is used when the Big Endian Support option is selected.

3.Ports are active-High unless otherwise specified.