This Figure shows a block diagram of the implementation of the Aurora 8B/10B core.
The major functional modules of the Aurora 8B/10B core are:
•Lane Logic: Each GTP, GTX, or GTH transceiver (hereinafter called transceiver) is driven by an instance of the lane logic module, which initializes each individual transceiver and handles the encoding and decoding of control characters and error detection.
•Global Logic: The global logic module performs the bonding and verification phases of channel initialization. During operation, the module generates the random idle characters required by the Aurora protocol and monitors all the lane logic modules for errors.
•RX User Interface: The AXI4-Stream RX user interface moves data from the channel to the application and performs flow control functions.
•TX User Interface: The AXI4-Stream TX user interface moves data from the application to the channel and performs flow control TX functions. The standard clock compensation module is embedded inside the core. This module controls periodic transmission of the clock compensation (CC) character.