The following table shows the revision history for this document.
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Date |
Version |
Revision |
|---|---|---|
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10/19/2023 |
11.1 |
•Updated figures Figure 3-4 and This Figure. •Added guidance for avoiding long delays in assertion/de-assertion. |
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05/11/2022 |
11.1 |
•Updated the Example B: Receiving a Message with NFC Idles Inserted section. •Updated the Reset and Power Down section. •Updated the Simulation speed up section. |
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04/04/2018 |
11.1 |
•Added a note to the description in Appendix A. •Added a bullet about data loss at GT receiver output interface in Appendix C. |
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10/04/2017 |
11.1 |
•Added description for the C_DOUBLE_GTRXTESET parameter. |
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04/05/2017 |
11.1 |
•Added support to generate Aurora without GT for UltraScale and UltraScale+ devices. |
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10/05/2016 |
11.0 |
•Removed the Example design directory structure due to the updates in Vivado flows for 2016.3 to support Windows shorter paths. |
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06/08/2016 |
11.0 |
•Added Reference to GT_Debug_Flowchart in AR 57237. •Updated C_EXAMPLE_SIMULATION usage description. |
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04/06/2016 |
11.0 |
Updated the support for tested development boards. |
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11/18/2015 |
11.0 |
Added support for UltraScale+ families. |
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09/30/2015 |
11.0 |
•Removed BUFG on the drpclk_in signal in the core and added in example design. •Added description of Figure 2-4 in the Port Description section. •Added links to the web page for performance and utilization characteristics. |
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04/01/2015 |
11.0 |
General Changes •Added GT location selection option for the UltraScale™ device section. •Modified AXI4-Stream information. •Grouped Flow control ports into the AXI4-Stream interface. •Updated Reset section. •Moved Clock Compensation section to Chapter 3, Designing with Core. •Added Single/Differential clocking option for GTREFCLK and core INIT_CLK. •Removed do_cc signal throughout. •Moved all of the material in the Core Features chapter to the end of Chapter 3, Designing with the Core. Deleted Chapter 4. •Changed reset to reset_pb, s_axi_ufc_tx_req to s_axi_ufc_tx_tvalid, usr_clk to user_clk, tx_reset to tx_reset_pb, and rx_reset to rx_reset_pb, s_axi_ufc_tx_ms to s_axi_ufc_tx_tdata, s_axi_ufc_tx_ack to s_axi_ufc_tx_tready, s_axi_tx_ready to s_axi_ufc_tx_tready, s_axi_tx_tdata to s_axi_ufc_tx_tdata, s_axi_nfc_req to s_axi_nfc_tx_tvalid, s_axi_nfc_nb to s_axi_nfc_tx_tdata, s_axi_nfc_ack to s_axi_nfc_tx_tready, s_axi_nfc_ack to s_axi_nfc_tx_tvalid, m_axi_rx_snf to m_axi_nfc_tx_tvalid, m_axi_ufc_rx to m_axi_ufc_rx_tdata, m_axi_tx_fc_nb[0:3] to m_axi_nfc_tx_tdata[0:3]. •Removed do_cc information. •Added the Single Ended option material throughout. •Changed IBUFDS to IBUFDS_GTE. Chapter 2: Product Specification •Modified TX User interface description. •Updated Figure 2-4, Figure 2-7, Figure 2-8, Figure 2-12, Figure 2-13, Figure 2-14, Figure 2-16, Figure 2-17, Figure 2-18, Figure 2-19, Figure 2-22, Figure 2-23, and Figure 2-26. •Removed paragraph about AXI4-Stream signal sampling. •Added information about s_axi_tx_tkeep. •Added reset and user_clk ports to Figure 2-7 and Figure 2-13. •Removed Data Strobe section. •Added heading rows UFC_S_AXIS_TX and UFC_M_AXIS_RX to Table 2-11. •Modified some clock domains in Table 2-16. •Modified m_axi_ufc_rx_tvalid description. •Deleted m_axi_ufc_rx_tvalid and m_axi_ufc_rx_tlast from Figure 2-22. •Adding heading rows NFC_S_AXIS_TX and NFC_M_AXIS_RX to Table 2-14. •Modified Figure 2-23: Transmitting an NFC Message. |
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04/01/2015 (continued) |
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Chapter 2: Product Specification (continued) •Added Important note about ports in the Transceiver Interface section. •Added rows for gt<lane>_txinhibit_in/gt_txinhibit and gt_pcsrsvdin to Table 2-18: Transceiver Ports. •Added notes 11 and 12 to Table 2-18: Transceiver Ports •Added 7 rows to Table 2-20: Added text about the Single Ended GT REFCLK and Single Ended INIT CLK options to Table 2-20. gt_qpllrefclk_quad<quad>_out, gt<quad>_qplllock_in, gt<quad>_qpllrefclklost_in, gt_qpllclk_quad<quad>_in, gt_qpllrefclk_quad<quad>_in, gt_qpllreset_out, tx_out_clk. •Changed “clock cycles” to “time period” throughout. •Extensively revised the Clock Compensation section. Removed Figures 2-28 and 2-29. Relocated after the Hot-Plug Logic section in Chapter 3 |
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Chapter 3: Designing with the Core •Moved all of the material in Chapter 4: Core Features to the end of this chapter. •Added a note about the Single Ended option to the Shared Logic section. •Updated Figure 3-11. Chapter 4: Design Flow Steps •Updated all Vivado IDE figures to version 11.0. •Updated Recommended note in the Lane Assignment section. •Added Starting GT Quad and Starting GT Lane options. •Added six rows to Table 4-1: Column Used, Starting GT Quad, Starting GT Lane, GT Refclk Selection, Single Ended INIT CLK, and Single Ended GTREF CLK. •Added notes about IP integrator and data and flow control ports to Core Generation section. Appendix B: Migrating and Upgrading •Updated Overview of Major Changes section. •Updated Figure B-3: AXI4-Stream Signals. |
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10/01/2014 |
10.3 |
•Added new v10.3 core features and attributes •Rearranged content to consolidate topics and better conform to template |
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06/06/2014 |
10.2 |
•Added information about migrating transceiver ports to UltraScale devices. |
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06/04/2014 |
10.2 |
•Added User Parameter information. •Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports |
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04/02/2014 |
10.2 |
•Added UltraScale architecture support. •Updated init_clk frequency requirements. •Added little endian support to User Data, NFC and UFC interfaces. |
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12/18/2013 |
10.1 |
•Added transceiver debug ports. •Updated all screen captures. •Updated all signals in figures to lowercase. |
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10/02/2013 |
10.0 |
•Added new chapters: Simulation, Test Bench and Synthesis and Implementation. •Added shared logic and transceiver debug features. •Updated directory and file structure. •Updated resource utilization tables. •Added information about hot-plug logic. •Updated screen captures for Figures 5-1, 5-2, 5-3, 5-4, 5-5, 8-1 and B-3. •Changed all uppercase signal names to lowercase. •Updated Migrating and Upgrading appendix. |
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06/19/2013 |
9.1 |
•Revision number advanced to 9.1 to align with core version number. •Updated for Vivado™ Design Suite v2013.2 and ISE™ Design Suite v14.6. •Aurora 8B10B v9.0 core is updated to Aurora 8B10B v9.1 based on revision guidelines. |
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03/20/2013 |
3.0 |
•Updated for Vivado Design Suite and core version 11.0 •Modified Appendix C, Debugging with transceiver debug details. •Updated screen captures in Chapter 5, Chapter 7, and Appendix B. •Removed ISE, CORE Generator™, UCF, Virtex™-6, and Spartan™-6 material. •Updated Reset waveforms. •Updated Directory and File Structure. •Created lowercase ports for Verilog. |
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12/18/2012 |
2.0.1 |
•Updated for Vivado Design Suite v2012.4 and ISE Design Suite v14.4. •Modified maximum and minimum latency. •Added many new signals to Table 2-22, Transceiver Ports. •Updated screen captures in Chapter 5, Chapter 7, and Appendix B. •Modified Appendix C, Debugging |
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10/16/2012 |
2.0 |
This release supports core version 8.3 with Vivado Design Suite v2012.3 and ISE Design Suite v14.3. Major changes include: •Updated screen captures for Figures 5-1, 5-2, 7-2, 8-1, 8-2, 8-3, 8-4, 10-2, and B-3. •Added steps for Generating the Core in Chapter 7. •Added Artix™-7 device support. •Added GTH transceiver support. •Added LOOPBACK[2:0] and GT_RESET ports to Table 2-22. •Replaced IBUFDS_GTXE1 to IBUFDS_GTE2 in Figure 3-2. •Removed Design Constraints section in Chapter 6. •Added Clock Frequencies, I/O Placement, and I/O Standard and Placement sections. |
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07/25/2012 |
1.0 |
•Initial Xilinx release. This release supports core version 8.2 with Vivado™ Design Suite v2012.2. This document replaces UG766 and DS797. |