With the transceiver being the critical building block in the Aurora 8B/10B core, debugging and ensuring proper transceiver operation is very important.
1.Transceiver attribute check:
Transceiver attributes must match with the silicon version of the device being used on the board. Apply all applicable workarounds and Answer Records given for the respective silicon version.
2.GT REFCLK and GT PLL LOCK check
A low-jitter differential clock must be provided to the transceiver reference clock. Check and make sure the REFCLK location constraints are correct with respect to the board schematics. REFCLK should be active and should meet the phase noise requirements of the transceiver.
The transceiver locks on to the incoming GT REFCLK signal and asserts the PLL0LOCK signal. If PLL0LOCK is toggling periodically, check that the FSM reset done signals are toggling. Make sure that the GT PLL attributes are set correctly and that the transceiver generates the txoutclk with the expected frequency for the given line rate and datapath width options. Note that the Aurora 8B/10B core uses Channel PLL (CPLL) in the generated core for AMD Virtex™ 7 and Kintex™ 7 FPGA GTX and GTH transceivers and PLL0/PLL1 for Artix™ 7 FPGA GTP transceivers. Check the transceiver power supply MGTAVCC value.
3.Transceiver TX/RX FSM RESETDONE check
The Aurora 8B/10B core uses sequential reset mode; all of the transceiver components are reset sequentially, one after another. The txresetdone and rxresetdone signals should be asserted at the end of the transceiver initialization. In general, rxresetdone assertion takes longer compared to the TXRESETDONE assertion. Check if user_clk and sync_clk are connected properly. Make sure the gt_reset signal pulse width duration complies with the respective transceiver guideline. Probe the signals and FSM states from the RX/TX STARTUP FSM module. If the RX/TX fsm_resetdone signals are asserted and the partner is reprogrammed, GTRXRESET should be asserted manually if hot-plug logic is disabled.