The transceiver generates txoutclk based on the line rate and lane-width parameters. The user_clk signal is generated from txoutclk and is used by the Aurora 8B/10B core to clock FPGA logic. Therefore, ensure that user_clk is generated properly with the expected frequency from txoutclk. If user_clk frequency is not in the expected range, check the frequency of the transceiver reference clock and verify the transceiver PLL attributes.