The Aurora 8B/10B core expects all clocks to be stable. If clocks are generated using the MMCM, ensure that the reset inputs are held High until the generated clock is stable. It is recommended to stop the output clock from the MMCM until it is locked. For cores generated with a 4-byte lane width in Artix 7 devices, the MMCM is used to generate user_clk and sync_clk. Make sure that the TX_LOCK output from the Aurora 8B/10B core is inverted and connected to MMCM_RESET. If MMCM_LOCK is toggling periodically, check that the TX_STARTUP_FSM module is restarting and probe the signals and states of the FSM.