shows the example design for the core using a device-specific transceiver (AMD UltraScale+™ /AMD UltraScale™ architecture, 7 series or AMD Zynq™ 7000).
Figure 1. Core Example Design HDL Using a Device-Specific Transceiver
The top level of the example design ( <component_name>_example_design
) creates a specific example that can be simulated, synthesized, implemented, and if
required, placed on a suitable board and demonstrated in hardware. The top level of the
example design performs the following functions:
- Instantiates the block level HDL
- Instantiates shared logic if shared logic in the example design is selected (see Shared Logic for more information)
- A transmitter elastic buffer
- GMII interface logic, including IOB instances
Note: The optional transceiver control and status ports
are not shown here. These ports have been brought up to the <component_name> module
level.