1G Ethernet PCS/PMA or SGMII with Ten-Bit Interface - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

When used with the Ten-Bit Interface (TBI), the core provides the functionality to implement the 1000BASE-X PCS sublayer (or to provide SGMII support) with use of an external SerDes. TBI mode is not supported for 2500BASE-X or 2.5 SGMII data rates.

Figure 1. Core Block Diagram with TBI Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.4 PCS Receive Engine and Syncronization PCS Receive Engineand Syncronization Sheet.5 Sheet.6 Optional PCS Management Optional PCSManagement Sheet.7 GMII Block GMII Block Sheet.8 8B/10B Encoder 8B/10BEncoder Sheet.9 8B/10B Decoder 8B/10BDecoder Sheet.10 RX Elastic Buffer RXElasticBuffer Sheet.11 Sheet.12 Sheet.13 TBI Block TBI Block Sheet.14 Sheet.15 IOBs IOBs Sheet.17 X12781 X12781 Sheet.18 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.19 GMII to MAC GMIIto MAC Sheet.20 MDIO Interface MDIOInterface Standard Arrow.14 Standard Arrow.47 Standard Arrow.12 Standard Arrow.4 Sheet.2 Optional Auto-Negotiation OptionalAuto-Negotiation Standard Arrow.5 Sheet.3 PCS Transmit Engine PCS TransmitEngine Arrow Standard Right.13 Standard Arrow.15 Standard Arrow.16 Standard Arrow.17 Standard Arrow.34 Standard Arrow.35 Standard Arrow.23 Sheet.16 TBI to external SERDES TBI to external SERDES Arrow Standard Right.21 Arrow Standard Right.22 Standard Arrow.28 Standard Arrow.33

The optional TBI is used in place of the device-specific transceiver to provide a parallel interface for connection to an external PMA SerDes device, allowing an alternative implementation for families without device-specific transceivers. In this implementation, additional logic blocks are required in the core to replace some of the device-specific transceiver functionality. These blocks are surrounded by a dashed line (see the above figure). Other blocks are identical to those previously defined.

Versal, UltraScale+, Zynq UltraScale+ MPSoC, UltraScale,Zynq 7000 , AMD Artix™ 7, Zynq 7000, and AMD Virtex™ 7 devices do not support the TBI. AMD Kintex™ 7 devices support TBI at 3.3 V or lower.