7 Series and Zynq 7000 Device LVDS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

This section provides guidelines for creating synchronous SGMII designs using Zynq 7000 and 7 series device LVDS. Supported devices are shown in the following table. This mode enables direct connection to external PHY devices without the use of an FPGA transceiver. An example implementation is shown in the following figure.

Table 1. Devices Supporting SGMII over LVDS
Family Supported Devices
Zynq 7000

-2 speed grade or faster for XC7Z010/20 devices and -1 speed grade or faster for XC7Z030/45/100 devices

Virtex 7

-2 speed grade or faster for devices with HR Banks or -1 speed grade or faster for devices with HP banks

Kintex 7

-2 speed grade or faster for devices with HR Banks or -1 speed grade or faster for devices with HP banks

Artix 7, Spartan 7 -2 speed grade or faster

For information about the SGMII over LVDS example design see Synchronous SGMII over LVDS Example Design (Applicable for Non-Versal Devices).

A detailed understanding of 7 series FPGA Clocking Resources and SelectIO Resources is useful to understand the core operation. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) and 7 Series FPGAs Clocking Resources User Guide (UG472).

Figure 1. Example Design for SGMII over LVDS Solution (7 Series and Zynq 7000) Clocking Logic refclk125_p refclk125_n clk125 clk104 clk208 clk625 LVDS Transceiver rxn rxp txn txp <component_name>_example_design SGMII Adaptation Module GMII-Style 8-bit I/F X12959 EncryptedRTL <component_name>_block