8B/10B Encoder - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
PG047
Release Date
2023-11-01
Version
16.2 English

The implemented 8B/10B coding scheme is an industry standard, DC-balanced, byte-oriented transmission code ideally suited for high-speed local area networks and serial data links. As such, the coding scheme is used in several networking standards, including Ethernet. The 8B/10B Encoder block is taken from AMD Application Note, Parameterizable 8B/10B Encoder (XAPP1122) provides two possible approaches: a choice of a block RAM-based implementation or a LUT-based implementation. The LVDS example design uses the LUT-based implementation, but the application note can be used to show how to swap this for the block RAM-based approach if this better suits the device logic resources.

The following files describe the 8B/10B Encoder:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/

synth/lvds_transceiver

<component_name>_encode_8b10b_pkg.v

<component_name>_encode_8b10b_lut_base.v